RISC-V is an open source hardware instruction set originally developed at UC Berkeley. It supports 3 word widths, 32, 64, 128 bits. One of its characteristics is to have a subset of compressed instructions utilizing 16 bits, used to reduce program size when intermixed with the regular instructions. In this project, your team will design the hardware component (mini micro processor) required to execute some of these instructions. This project is to be performed either individually or by a group of at most 4 students. For this project, you will design (using VHDL or schematics capture and components library) and simulate an 8- bit processor (8-bit registers), which includes four registers R0, R1, R2 and R3, able to execute the instructions similar to a subset of the compressed RISC-V instruction set as shown on the table below. Table RISC-V Compressed Instruction subset